Logic gates and TTL / CMOS families

A logic gate takes bits (0 and 1) and outputs a bit by a fixed rule — the truth table. In lab you do not leave that table on paper: you build it with a TTL or CMOS IC.

Source

Rojas, ch. 3 — gates and algebra and Floyd, digital systems on CALETAS. Rojas exams usually allow 2-input gates only when you draw a circuit.

Analysis vs design

Analysis: you get the drawing → you write F = … and, if values are given, you compute 0 or 1.
Design: you get F = … → you draw AND / OR / NOT (or NAND / NOR if asked).
Same language, both directions. Lab will ask for both.

The six gates you must draw from memory

ANSI symbols (the AND “D” body is the site mark): lines on the left = inputs, line on the right = output.

Gate	Function	Output is 1 when…	Typical IC (TTL 74xx)
AND	F = A · B	every input is 1	7408
OR	F = A + B	at least one input is 1	7432
NOT	F = NOT A	the input is 0	7404
NAND	F = NOT (A · B)	the inputs are not all 1	7400
NOR	F = NOT (A + B)	every input is 0	7402
XOR	F = A XOR B	the inputs differ	7486

XNOR (F = NOT (A XOR B)) is 1 when the inputs are equal. That is even parity — the same idea as Hamming.

2-input tables

A	B	AND	OR	NAND	NOR	XOR	XNOR
0	0	0	0	1	1	0	1
0	1	0	1	1	0	1	0
1	0	0	1	1	0	1	0
1	1	1	1	0	0	0	1

NOT (1 input): 0 → 1, 1 → 0. The bubble on the symbol is inversion.

NAND and NOR are universal

NAND alone (or NOR alone) can build AND, OR, and NOT. Exams ask “implement with 2-input NAND” because 7400 is the common chip and it proves De Morgan. That is finished in Boolean algebra.

Logic families: TTL and CMOS

The gate on paper is the same. The package is not: TTL and CMOS are two ways to make 0 and 1 in silicon. Midterm II and lab ask for the family, not only the symbol.

Platform	Role	Strength	Limit
TTL (74xx, 74LS)	Bipolar transistors. Classic 5 V breadboard parts	Rugged, usable output current, huge Proteus library	Higher static power; HIGH is not a full 5 V; do not mix blindly with 4000 CMOS
CMOS (4000, 74HC)	MOSFETs. Low power, dominant today	Almost no static current; 4000 series VDD from ~3 V to 15 V	Floating inputs oscillate; ESD sensitive; 4000 is slower than 74LS
74HCT (TTL-compatible CMOS)	CMOS with TTL-like input thresholds	Lets a 74LS output drive an HC-style input at 5 V	Still a 5 V story; it is not a 3.3 V ↔ 5 V translator

What 0 and 1 mean in volts (5 V)

Family	Max VIL (still 0)	Min VIH (already 1)	Typical LOW / HIGH out
TTL 74LS	0.8 V	2.0 V	~0.35 V / ~3.4 V
CMOS 74HC @ 5 V	1.5 V	3.5 V	~0 V / ~5 V
CMOS 4000 @ 5–15 V	~30 % of VDD	~70 % of VDD	nearly rail to rail

A TTL HIGH (~3.4 V) may not count as 1 for 74HC (wants ≥ 3.5 V). Lab fix: 74HCT, or do not mix.

Breadboard rules

1. TTL 74LS is powered at 5 V. Never 12 V.
2. CMOS 4000 allows a wider VDD, but inputs must never float: tie them to VDD, GND, or a real signal.
3. Fan-out: one LS output drives about 20 LS inputs; HC drives many more.
4. In Proteus pick the same prefix as the parts bin: 74LS08, not a 4081, if the report asks for TTL.

Prefixes on the chip and in Proteus

• 74xx — original TTL (rarely stocked now).
• 74LS — Low-power Schottky. Default for gate labs.
• 74HC — High-speed CMOS. Same pinout as 74, different electrical family.
• 74HCT — HC with TTL input thresholds.
• 40xx / 45xx — “old” CMOS (CD4000). Different pinout from 74.

Typical 74LS00 DIP-14 (four 2-input NANDs): VCC pin 14, GND pin 7.

From symbol to circuit

Messy exam function (before simplifying):

x = (NOT A)·B + A·(NOT B)·C + A·B·C

1. Draw 2-input AND / OR / NOT (split a 3-input AND into two 2-input ANDs).
2. Count gates — that is what they grade if they ask for “minimum”.
3. Only then simplify with algebra or Karnaugh, and redraw.

4-bit parity (cascaded XOR) is the same language as Hamming.

Next step

Continue with truth tables and canonical forms. XOR and parity come back in the Hamming assignment (partial I; sidebar Assignments).

Mark the unit on the study path.